| 摘要 |
PURPOSE:To improve the accuracy of a system locking by implementing half killer processing only for a predetermined blank pulse period and synthesizing the result with a horizontal synchronizing signal other than the blank pulse period to obtain the horizontal synchronizing signal for all the period. CONSTITUTION:A blank pulse generating section 2 receives a comparison signal S4 resulting from frequency-dividing a system clock for a horizontal period in addition to a vertical synchronizing signal S3 and generates a blank pulse G coincident with a period of an equivalent pulse and a vertical synchronizing pulse within the vertical blanking period. An edge detection section 3 detects an edge from the composite synchronizing signal S2 and the result is fed to a horizontal synchronizing signal extract section 4. A half killer processing circuit 4b of the extract section 4 implements half killer processing based on a pulse G and an edge signal E to eliminate the vertical synchronizing signal and the equivalent pulse for the period of the pulse G and to obtain an edge signal of the horizontal synchronizing signal. Furthermore, a horizontal synchronizing signal extract section 5 uses the pulse G to mask the signal S2 and to obtain the horizontal synchronizing signal other than the mask period. Then an OR circuit 6 synthesizes outputs of the extract section 4 and the detection section 5. |
