| 摘要 |
<p>PURPOSE:To realize a frame phase synchronization circuit whose memory capacity is small, in which two address generating sections are not required for addresses of the memory and the occurrence of slip is prevented. CONSTITUTION:A memory 7 whose capacity is one frame is used for the circuit. Furthermore, a transmission signal from an input system is phase-shifted variably and the resulting signal is given to the memory. The circuit is provided with 1st variable phase shift means 1, 3 whose phase shift enable range depends on a phase fluctuation of an input system clock with respect to a received system clock and with 2nd variable phase shift means 2, 4 variably phase- shifting the input system frame pulse and giving the result to a write address generating section 6 whose phase shift range is decided similarly to the case with the 1st variable phase shift means, and also with a phase shift quantity control means 5 which detects the relation between the write phase and the read phase with respect to the memory to decide the common phase shift quantity of the 1st and 2nd variable phase shift means.</p> |
