| 摘要 |
PURPOSE:To provide a delay phase detector whose circuit configuration is simple and miniaturized into a monolithic integrated circuit. CONSTITUTION:The phase detection circuit 10 is provided with a frequency divider DIV generating a 1st reference signal Rcos, a shifter SFT generating a 2nd reference signal Rsin obtained by phase-shifting the 1st reference signal Rcos by pi/2, a 1st logic circuit EX1 and a 2nd logic circuit EX 2 exclusively ORing a received signal IF and the 1st reference signal Rcos and ORing exclusively the received signal IF and the 2nd reference signal Rsin. When outputs of the logic circuits EX1, EX2 are logical 1, a 1st counter CT1 and a 2nd counter CT2 count a clock CLK respectively and latch circuits LT1, LT2 latch respectively the count and a phase arithmetic circuit PHS calculates a phase difference between the received signal and the reference signal from the latched digital value. |
