| 摘要 |
PURPOSE: To substantially reduce delay added to clock signals for clock inputting the output of a first circuit to the input of a second circuit. CONSTITUTION: The output of the first circuit is connected to a data line and the first circuit is constituted of an element provided with a selected set of design parameters such as the dimension of a transistor and an orientation state, etc., for instance. The second circuit is connected to the data line and receives the clock signals generated by a signal delay circuit 110. The signal delay circuit 110 receives output enable signals, responds to the output enable signals after a delay period and generates the clock signals. At least a part of the signal delay circuit, for instance the transistors 114 and 116, uses the element provided with the selected set of the design parameters used in the first circuit. Thus, when processing variation affects the electric characteristics and speed of the transistor in the first circuit, the same processing variation proportionally affects the electric characteristics and speed of the transistor inside the delay circuit. |
