| 摘要 |
<p>PURPOSE:To obtain an on-chip decoder/wait state generator imparting the internal address decoding for the interface processings with plural external memory devices of various kinds of speed by providing a chip select decoder provided with a means enabling the first memory device of an external memory. CONSTITUTION:This processor is composed of a DSP 1100 provided with a parallel interface unit 4000 including a chip select decoder enabling an external memory device so that it may be selected. In the chip select decoder, a parallel interface output (PIO) chip selection control register designating plural memory constitutions using plural memory devices of different speed for the use in shared memory circumstances is included. Further, in the parallel interface unit 4000, a wait status controller provided with a PIO wait control register holding the operation of the processor till the selected memory device get ready is included.</p> |
