发明名称 PLL FREQUENCY SYNTHESIZER SYSTEM
摘要 PURPOSE:To improve a CN ratio, etc., by phase-comparing the difference frequency between a signal from a voltage control oscillator and a fixed frequency signal with the divided signal of a comparative signal and by controlling the voltage control oscillator by the phase error output. CONSTITUTION:A signal of frequency (fr) is divided by programmable counter 15 by M and phase-compared with the difference frequency from mixer 12, and local oscillation frequency fvco of voltage control oscillator 11 is controlled via LPF16 so that both frequencies will become equal each other. Therefore, fvco' is made to vary bit by bit through the variation of output frequency (f) of counter 15. For example, the variation in a step of 1KHz is caused by oscillator 7 for generating the 1st local oscillation frequency and the output of oscillator 11 is varied in a step of 100Hz till 1KHz. As a result, frequency fvco' varies in a step of 100Hz by variation DELTAM at dividing ratio M, and signals to be phase-compared 14 are within 10KHz + or - 500Hz, so that a CN ratio, etc., can be improved.
申请公布号 JPS5483754(A) 申请公布日期 1979.07.04
申请号 JP19770152047 申请日期 1977.12.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HORIIKE YOSHIO;INUI TOSHIAKI
分类号 H03L7/22;H03L7/23 主分类号 H03L7/22
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