| 摘要 |
An EEPROM cell structure includes two floating gate transistors (20, 22) separated by a select gate transistor (24) with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates (20B, 22B) of the two transistors are formed from a first polysilicon layer, the control gates (20C, 22C) of the two transistors are formed from a second polysilicon layer, and the select gate (24A) is formed from a third polysilicon layer. The channel length (24G) of the select transistor is fully self-aligned to the floating gate transistors (20, 22). A word line (28) is formed over the control gates and forms the select gate. The word line (28) runs generally perpendicular to bit lines (22A, 20A) which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.
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