| 摘要 |
PURPOSE:To obtain the output containing zero as well as to generate the false random pulse fearuring the circulating cycle of 2<n> by providing two units of the OR gate to the parallel output circuit in the shift register and also using the shift register of n-bit. CONSTITUTION:The false random pulse generator circuit uses the exclusive logical sum of parallel output H1-H4 of shift register 8 as the series input of register 8. In this pulse generator circuit, 1st OR gate 9a is provided to supply logic 1 to series input terminal 2 of the register when output H1-H4 of register 8 all become logic 0. Furthermore, 2nd OR gate 9b is installed to supply the signal of logic 0 to terminal 2 when the final bit among H1-H4 becomes logic 1 with all other bits of logic 0, along with inverter 10 provided between final bit output H4 and gate 9b. Then logic 0 is contained in the output of register 8, and the circulating cycle is set to 2<n> when the n-bit register is used. |
