发明名称 |
Method for fabricating self-aligned polysilicon contacts on FET source/drain areas |
摘要 |
Improved N-channel and P-channel field effect transistor device structure having self-aligned polysilicon pads contacts and a process for making such devices has been achieved. The doped polysilicon pad contact are formed over the source/drain areas of the field effect transistors and are used to form shallow self-aligned diffused contact to the source/drain areas. These polysilicon pads provide a low resistance ohmic contacts that are free from implant damage that would otherwise cause increased junction leakage current and are free of metal spiking at the source/drain area perimeter that would cause metal contact to substrate shorts. The increased area of the polysilicon pads over the source/drain area allows for relaxed design ground rule for the contact openings, making for a more manufacturable process for Ultra Large Scale Integration applications.
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申请公布号 |
US5432105(A) |
申请公布日期 |
1995.07.11 |
申请号 |
US19940308310 |
申请日期 |
1994.09.19 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
CHIEN, SUN-CHIEH |
分类号 |
H01L21/285;H01L21/8238;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/285 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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