| 摘要 |
1,123,641. Digital frequency measuring. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 31 March, 1967 [4 April, 1966; 10 March, 1967], No. 14998/67. Heading G4H. In apparatus for measuring the difference between an unknown frequency and a reference frequency the unknown frequency is sampled for polarity at recurring instants, the samples being translated into binary signals ("1" and "0") and combined in differently spaced pairs in modulo 2 adders, the outputs of which are applied to majority decision circuits to determine whether "1's" or "0's" preponderate, the outputs of the decision circuits then representing in binary code the frequency difference to be measured. If a frequency of F is sampled at the same frequency successive pairs of samples will have the same polarity, i.e. they will both be represented by "1" or by "0". If any pair of pulses is added in a modulus 2 adder the output will be "0". If a frequency F is sampled at half this frequency, alternate samples will have opposite polarity and the adder will give "1". For input frequencies between F and half F some adder outputs will be "1" and some "0", the maj ority indicating that the frequency is nearer F or nearer half F. In the apparatus described, Fig. 2, sampling is effected by a diode gate 2 actuated by clock pulses 3. These pulses are applied as shift pulses to a trigger chain 101-132. The sample pulses from gate 2 are applied to the first stage 101 and the outputs of subsequent stages 102, 104, 108 &c., are applied with the output of gate 2 to half-adders 11, 12, 13 &c. The output of gate 2 and the output of stage 102 represent two samples of a series having a frequency of F. Similarly the output of gate 2 and the output of stage 104 represent two samples of a series having a frequency of half F and so on. Each of the half-adders gives a succession of "1's" or "0's" indicating that the two input samples had different or the same polarity. Majority decision circuits 21, 22, 23 &c., determine which predominate in each adder output, and give a binary signal at 31, 32 &c. These output signals then represent the difference between the input signal and the centre frequency of the band-width of the system. The majority decision circuits (Fig. 3, not shown), each comprise an auxiliary shift register the outputs of which are gated together so that if the majority of signals in the register are "1's" the output will be "1" and if the majority are "0's" the output will be '' 0 ''. |
