System and method for accessing data in a computer system including a cache controller and a memory controller connected in parallel.

摘要

Disclosed is a personal computer system which eliminates an extra bus state for all memory cycles and I/O cycles that require main memory access. The computer system includes a cache controller disposed in parallel with a memory controller. A control signal is provided from the cache controller to the memory controller during a first bus state of a cache miss cycle to allow the memory controller to process the cycle. By generating the control signal during the first bus state, the memory controller can complete the cache miss cycle without incurring a penalty.