发明名称 METHOD AND APPARATUS FOR AUTOMATIC REDUCTION OF POWER CONSUMPTION OF CHIP
摘要 <p>PURPOSE: To automatically place a chip to a state where power consumption is reduced by making the chip monitor its own operation and placing the chip in the state where power is reduced in response to a monitoring process for judging that the chip is in a prescribed state. CONSTITUTION: A power consumption reduction logic 500 reduces the power consumption of an FDC by stopping internal clocks generated in a clock generation part 509 and adding power consumption reduction state signals (PD-STATE) to a circuit. An REG-ACCESS logic 501 judges whether or not one of the motors of the drive of a floppy disk is turned to a possible state, whether or not a FIFO is accessed at present by a read operation or a write operation and whether or not an MSR command register is read. The REG-ACCESS logic 501 outputs REG-ACCESS signals to an automatic power consumption reduction logic 503 and the logic 503 decides whether or not to place the FDC in a power consumption reduction state in response to the signals.</p>
申请公布号 JPH07168654(A) 申请公布日期 1995.07.04
申请号 JP19930070780 申请日期 1993.03.08
申请人 INTEL CORP 发明人 ANDORIYUU EMU BUOOKU
分类号 G06F1/04;G06F1/32;(IPC1-7):G06F1/32 主分类号 G06F1/04
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