发明名称 RE-SEQUENCE SYSTEM
摘要 <p>PURPOSE: To remove delay jitter in the re-sequence of the cell of a cell flow passing through the cascade connection of a first switching node(SN'), a buffer register(OB), and a second switching node(SN). CONSTITUTION: A re-sequence system includes a delay measuring circuit(DDM) constituted for measuring time delay received by each cell in a buffer register(OB) related with the buffer register(OB). Also, this system is provided with a means which transmits the measured delay of each cell to re-sequence means(TSG, IC, REG, SUB, and RSU) after the cell is switched by a second switching node(SN), and the time delay received by this cell is made equal to a difference between preliminarily decided constant time delay value and the transmitted delay.</p>
申请公布号 JPH07170275(A) 申请公布日期 1995.07.04
申请号 JP19940193303 申请日期 1994.08.17
申请人 ALCATEL NV 发明人 NEEDERUROOFU REO
分类号 H04Q3/00;G06F7/06;H04L12/54;H04L12/56;H04L12/66;H04Q3/52;H04Q11/04;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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