| 摘要 |
PURPOSE:To detect the lock of a PLL surely, even when a phase shift occurs owing to a slight change in speed. CONSTITUTION:Output signals CK1, FG1, FG1' and CK1' having phases different from those of a command pulse CK and a feedback pulse FG are generated in D flip-flops 31, 32, 41 and 42 on the basis of reference clock pulses CLK11 and CLK2. A phase-difference detecting circuit 3 counts the output signal CK1 between the rising edges of the output signal FG1. A phase-difference detecting circuit 4 counts the output signal FG1' between the rising edges of the output signal CK1'. Output signals S2 and S4 from multivibrators 35 and 45 triggered by the second bit output signals S1 and S3 of respective counters 33 and 43 are inputted to a NAND circuit 51. When the output signal S5 of the NAND circuit 51 is 'LOW', an LED 56 is lit judging that locking has occurred. |
