发明名称 |
Apparatus for simultaneously scheduling instruction from plural instruction streams into plural instruction execution units |
摘要 |
Disclosed is an information processor comprising multiple instruction setup units which fetch and decode instructions as the first half of the procedure in instruction pipelines, each of the instruction setup units being in charge of processing instruction streams. The decoded results are scheduled in instruction schedule units and sent to each corresponding function unit to be executed.
|
申请公布号 |
US5430851(A) |
申请公布日期 |
1995.07.04 |
申请号 |
US19920893466 |
申请日期 |
1992.06.04 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
HIRATA, HIROAKI;NISHIMURA, AKIO |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|