SEMICONDUCTOR STORAGE DEVICE, CLOCK-SYNCHRONOUS TYPE SEMICONDUCTOR DEVICE AND OUTPUT CIRCUIT

摘要

PURPOSE:To provide a cache DRAM provided with a command register capable of driving an output control signal at a high speed, storing the command data specifying many operation modes and internal conditions in a smaller occupation area and writing/reading from the outside. CONSTITUTION:A control signal output circuit 50 is provided with a first output drive transistor PD conducting according to a drive signal phi1 and discharging an output node 60 to a grounded potential level and a pull-up drive control circuit 72 generating a pull-up drive control signal becoming an activated state for a prescribed period when the first drive signal is inactivated. Further, the circuit 50 is provided with a pull-up drive circuit 74 becoming the activated state for the prescribed period according to the pull-up drive control signal and a second output transistor PU conducting in response to a drive signal phi2 from the pull-up drive circuit 74 and driving the output node 60 to a power source potential level for the prescribed period. Then, even when the output node 60 is wired-OR-connected to a signal line, the circuit 50 is made the inactivated state at a high speed by the drive transistor PU at the time of inactivation.