发明名称 |
Input limiting module for voltage signals of variable amplitude |
摘要 |
An input limiting circuit module (2) for voltage signals (1) of variable amplitude has a voltage divider (7) of controllable ratio formed by a field effect transistor and fixed resistor which operates in conjunction with a peak voltage sensor (8) which latter exerts a controlling influence on the divider ratio via a feedback connection. In this way all incoming signals (1) are subjected to a standardising process which restricts their amplitude but preserves their contour. A low pass filter (4) transfers the standardised signal to an output stage (5) in which its analogue form is converted to a digital equivalent of the same frequency (6) for further use.
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申请公布号 |
DE4344048(A1) |
申请公布日期 |
1995.06.29 |
申请号 |
DE19934344048 |
申请日期 |
1993.12.23 |
申请人 |
VDO ADOLF SCHINDLING AG, 60326 FRANKFURT, DE |
发明人 |
DUENSER, FRANZ, NUEZIDERS, AT |
分类号 |
G01D1/12;G01D3/02;G08C13/00;(IPC1-7):G08C13/00;G01D5/244 |
主分类号 |
G01D1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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