发明名称 Limiter circuit.
摘要 <p>Disclosed herein is a limiter circuit for limiting an output data to a limit value when an input data exceeds in value the limit value. The limiter circuit includes an encoder responding to the input data and producing a first data indicative of the number of significant digits of the value of the input data, a comparator comparing the first data with a second data indicative of the number of significant digits of the limit value, and a decoder responding to the second data and producing a third data indicative of the limit value. One of the input data and the third data is selected and outputted as the output data through a selector responding to a comparison output of the comparator.</p>
申请公布号 EP0660226(A2) 申请公布日期 1995.06.28
申请号 EP19940120296 申请日期 1994.12.21
申请人 NEC CORPORATION 发明人 ISHIDA, HIDEO, C/O NEC CORPORATION
分类号 G06F7/00;G06F7/02;G06F7/48;G06F7/74;(IPC1-7):G06F7/48 主分类号 G06F7/00
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