Line decoding circuit for a memory working with low power voltages.

摘要

The invention relates to a decoding circuit (200) which can operate with low selection voltages. Selection transistors (9) are connected in series between an input terminal (3) and an inverter (10) whose output is connected to an output terminal (4). The inverter (10) includes two transistors of type P (11) and N (12) respectively, mounted in series. The control gate of the first transistor (11) is connected to the selection transistors (9), whilst the control gate of the second transistor (12) is connected to the input terminal (3).