| 摘要 |
<p>The present invention is a reduced iteration decoder circuit and method for computing error-locator sequence values ( lambda at 132) for use in the correction of bit errors in Reed-Solomon or BCH coded information (r at 111). By utilizing special properties of Reed-Solomon code and BCH codes, the decoder circuit of the present invention can detect n symbol errors using approximately n mathematical iterations (in 120) with substantially reduced decoding processing time. A further reduction of decoding time is achieved by the performance of a substantial portion of the decoding processing in a parallel manner. The present invention may be utilized in digital communication systems and data storage systems or other information systems where Reed-Solomon or BCH encoding is utilized. <IMAGE></p> |
