| 摘要 |
<p>A modulator for a clock pulse generator receives clock pulses from a clock pulse source (18, 32), which clock pulses exhibit a reference phase. Delay circuitry (10) is connected to the clock pulse source (18) and includes n tap connections (20, 22, 24, 40), each connection providing a clock pulse that is delayed by a different phase delay from the reference phase. A multiplexer (34) is connected to each of the n tap connections (20, 22, 24, 40) and provides an output manifesting the clock pulses. A selector circuit (26) controls the multiplexer (34) to sequentially connect any sequence of different ones of the n tap connections (20, 22, 24, 40) to the multiplexer's output (28), whereby the output (28) manifests a series of clock pulses which have different phase displacements from the reference phase. <IMAGE></p> |
