A clock recovery circuit for serial digital video.

摘要

A control circuit for use with a phase locked loop in a digital video receiver. The digital receiver accepts a serial digital input signal which can comprise composite or component video signals. The phase locked loop comprises a phase detector, a loop filter, and a voltage controlled oscillator (VCO) and includes a divide-by-two modulus divider coupled to the output of the VCO. The VCO has an oscillation frequency control port and the divider has a frequency select port. The control circuit includes an automatic fine tuning and frequency sweeping stage which is coupled to the output of the loop filter and the oscillation frequency control port. The tuning and frequency stage provides temperature drift correction for the VCO. In addition, the tuning and frequency stage "sweeps" the oscillation frequency of the VCO to aid in "locking" the phase locked loop to the phase or frequency of the input signal. Once locked, timing signals and digital data can be extracted from the input signal. The control circuit also includes a video signal detector stage for detecting whether the input signal comprises a composite video signal or a component video signal. The video signal detector stage produces an output signal which controls the modulus of the divider in the phase locked loop.