| 发明名称 |
Method and interlevel dielectric structure for improved metal step coverage. |
| 摘要 |
A VLSI contact formation process in which a nitride layer is used to stop a wet oxide etch. An anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a "Y"-shaped profile. <IMAGE> |
| 申请公布号 |
EP0660392(A1) |
申请公布日期 |
1995.06.28 |
| 申请号 |
EP19940308635 |
申请日期 |
1994.11.23 |
| 申请人 |
STMICROELECTRONICS, INC. |
发明人 |
NGUYEN, LOI;SUNDARESAN, RAVISHANKAR C/O CHARTERED MFG PVT LTD |
| 分类号 |
H01L21/302;H01L21/3065;H01L21/316;H01L21/318;H01L21/3213;H01L21/768;H01L23/522 |
主分类号 |
H01L21/302 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
