| 摘要 |
According to the present invention, integrated circuitry provides for the ability to selectively introduce delays into the timing of the integrated circuit, without the expense and time associated with methods used in the prior art. As a minimum, a fuse element having at least one fuse and a transistor element having at least one transistor are placed in parallel to each other between a voltage supply of a gate of the integrated circuit and a corresponding voltage supply of the integrated circuit. When the fuse element is intact, the fuse element provides a relatively low resistance path from the voltage supply of the gate and the corresponding voltage supply of the integrated circuit. However, upon blowing the fuse element, this low resistance path is no longer available. An increased resistance path through the transistor element must be used, and the integrated circuit is slowed down accordingly. The amount of delay introduced to the delay element is a function of the values of the transistors in the transistor element.
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