| 摘要 |
The object of the present invention is to provide a nonvolatile memory wherein stored data can be properly read at power-on even if the memory is designed to achieve faster operating speeds by performing operations such as bit line charge-up by detecting an address signal change and the turning-on of the power. A nonvolatile semiconductor memory in which, after a write or an erase operation, a read operation for verification is performed by applying a voltage at a first verification level V2, which is lower than an applied voltage for a normal read operation, or a voltage at a second verification level V3, which is higher than the applied voltage V1, the nonvolatile semiconductor memory comprising: an address-transition-detection circuit 1; a supply voltage detection circuit 3 for generating an initialization transition signal at the rise of a supply voltage when the supply voltage has reached a first supply voltage transition threshold level V4 higher than the first verification level V2; and a transition operation circuit 2 for performing operations such as bit line charge-up in accordance with the address transition signal and initialization transition signal.
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