| 摘要 |
A data retention circuit prevents erroneous data from being written into a backup RAM, even when a software upset occurs so that a secure data retention can be obtained in a backup RAM of a game machine. A backup chip select signal output from an address decoder, outputs of an enable circuit, and a software upset detection circuit are used to enable a backup memory write process. The enable circuit outputs an enable signal only when a predetermined ID code signal sequence is supplied from a CPU. When inconsistency between an access pattern, a read, and a write signal occurs, the software upset detection circuit outputs a software upset detection signal. An AND gate blocks a supply of the backup chip select signal to the backup memory according to a combination of the software upset detection signal and the enable signal.
|
