发明名称 Single-chip microcontroller with efficient peripheral testability
摘要 A single-chip microcontroller (30) includes a central processing unit (CPU) (31) and several memory-mapped peripherals (32, 33, 34, 35) connected to internal address (37) and data (38) buses. The microcontroller (30) includes a test port (40) for receiving test data and providing the test data to the address (37) and data (38) buses to access the memory-mapped peripherals (32, 33, 34, 35) directly. The microcontroller (30) thus allows testing of the memory-mapped peripherals (32, 33, 34, 35) without CPU overhead, significantly reducing test time. The test port (40) includes a shift register (44) which selectively updates address high, address low, and data fields using the test data so that a field need not be re-entered if it doesn't change between test cycles. The test port (40) receives the test data and test control signals via signal lines shared with a general purpose input/output (GPIO) port (33) and requires only one independent control signal line.
申请公布号 US5428770(A) 申请公布日期 1995.06.27
申请号 US19930114597 申请日期 1993.08.31
申请人 MOTOROLA, INC. 发明人 GARNER, ROBERT E.
分类号 G06F11/273;(IPC1-7):G06F11/30 主分类号 G06F11/273
代理机构 代理人
主权项
地址