| 摘要 |
A process is provided for forming a bipolar transistor and a structure thereof. In particular a single polysilicon self-aligned process for a bipolar transistor having a polysilicon emitter is provided. A sacrificial layer defining an opening is provided in a device well region of a substrate, and, after forming a self-aligned base region within the opening, emitter material is selectively provided in the opening to form an emitter-base junction. The sacrificial layer functions as a mask for ion implantations to form the base region, and if required, an underlying local collector region. The sacrificial layer is removed, to expose the well region adjacent sidewalls of the emitter structure. A self-aligned link region implant may be performed before forming isolation on exposed sidewalls of the emitter structure. Extrinsic base contacts are formed in the surface of the surrounding well region. The sacrificial layer is preferably a material which may be removed by an etch process with high selectivity to the substrate to avoid damage on overetching, for improved manufacturability and reliability. The process flow is compatible with CMOS processing, and applicable to bipolar CMOS integrated circuits.
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