发明名称 Closed-loop peak detector topology
摘要 The present invention is a closed loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals. In reset mode, the second current source discharges the capacitor until the output voltage is equal to a baseline voltage VREF. In peak detect mode, the first current source charges the capacitor when the instantaneous value of the output signal is less than the input signal. The peak detector uses the input signal to pump up the output voltage to the most positive value of input signal. In hold mode, the current sources are disabled. The capacitor maintains a nearly constant amount of charge. Thus, the output voltage is equal to the peak voltage of the input signal stored on the capacitor.
申请公布号 US5428307(A) 申请公布日期 1995.06.27
申请号 US19930140757 申请日期 1993.10.20
申请人 SILICON SYSTEMS, INC. 发明人 DENDINGER, STAN
分类号 H03K5/007;G01R19/04;H03D1/18;H03K5/1532;(IPC1-7):G01R19/04;H03K5/24 主分类号 H03K5/007
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