Bias generator for low ground bounce output driver

摘要

A bias generator circuit provides a bias control signal to the gate of a PMOS transistor which has been added to the inverter which drives the final NMOS pull-down transistor of a CMOS output driver circuit. The bias generator circuit includes a constant current source flowing from the positive supply. The bias generator circuit also includes a current difference circuit containing a resistive divider which drives the gate of an NMOS ballast transistor. This ballast transistor has process/voltage/temperature (PVT) characteristics corresponding to those of the final NMOS pull-down transistor in the CMOS output driver. The channel length of the NMOS ballast transistor and the final NMOS pull-down transistor are drawn the same. The ballast transistor subtracts a PVT adjusted current from the constant current source to produce a PVT adjusted output charging current. A down current mirror includes two PMOS transistors which are mirrored in the inverter which drives the final pull-down transistor of the CMOS output driver circuit. Thus, when this inverter is turned on, the charging current which flows at its output will mirror the PVT adjusted charging current flowing in the down current mirror. This produces a PVT adjusted voltage ramp on the gate of the final NMOS pull-down transistor. This PVT adjusted voltage ramp provides two important benefits: significantly reduced ground bounce and output driver falling delay which is independent of existing PVT conditions.