| 摘要 |
PURPOSE:To lower the occurrence rate of a P-N junction defect in a memory cell region and to sufficiently lower a contact resistance in a peripheral circuit region. CONSTITUTION:A first contact hole for a bit line is formed in an interlayer insulating film 39, and a polysilicon film 40 is deposited inside the contact hole and on the interlayer insulating film 39. Then, the polysilicon film 40 is isotropically dry-etched by making use of a resist as a mask, and the interlayer insulating film 39 is etched by RIE. A second contact hole 39b is formed in the interlayer insulating film 39 in a peripheral circuit region 31b, and a laminated film 44 is formed inside the contact hole 39b and on the polysilicon film 40. Then, a filling material 45 is filled into the second contact hole 39b, the laminated film 44 and the polysilicon film 40 are patterned, and a bit line 46 is formed in a memory cell region 31a. Consequently, the occurrence rate of a P-N junction defect can be lowered, and a contact resistance can be lowered. |
