| 摘要 |
PURPOSE:To enhance the production yield of the semiconductor device by preventing the characteristic of a load PMOS transistor from becoming unbalanced due to the misalignment of a photolithographic operation when a source region and a drain region for the load PMOS transistor are formed. CONSTITUTION:A groove part 16a is formed in a silicon oxide film 15 which has been formed at the upper part of a gate electrode 9b for a drive NMOS transistor. A gate electrode 18a, for a load PMOS transistor, which is faced with a channel region 25a for the load PMOS transistor, a gate silicon oxide film 21a and the channel region 25a for the load PMOS transistor are formed in the groove part 16a. After that, silicon oxide films 17, 28 are filled on the channel region 25a for the load PMOS transistor. Thereby, impurities which are used to form a heavily doped region 24a for the load PMOS transistor and a Vcc potential line 26b are implanted in a self-aligned manner by making use of the silicon oxide films 27, 28 as a mask and without using a photolithographic technique. |
