| 摘要 |
1,070,910. Data processors. WESTERN ELECTRIC CO. Inc. Dec. 5, 1963 [Dec. 13, 1962], No. 48044/63. Heading G4A. In a data processor in which instructions are decoded in overlap relation, a transfer instruction is positioned one or more instructions before the final instruction of an instruction sequence to be transferred from and is executed prior to said final instruction. In this way accessing of the undesired final instruction is avoided on transfer, despite the overlapping. As described, a given instruction is dealt with in three machine cycles as follows: Cycle 1-a programme address register addresses the programme store (portion). Cycle 2-the addressed instruction is passed to a preliminary instruction register, the command portion of the instruction being then decoded in a preliminary decoder and the address portion passed to an address register. If the instruction is a transfer instruction, the address portion is then passed to the programme address register, otherwise the latter is incremented by one and the address portion used instead to address a data store (portion). Cycle 3-the command portion is passed to a final instruction register from which it is decoded in a final decoder which gates data between the data store (portion) and a selected one of three data registers, via a buffer register. Successive instructions are overlapped in that cycle 1 for a given instruction is the same cycle as cycle 2 for the instruction before and cycle 3 for the instruction before that. Data address indexing is mentioned. |
