A phase synchronization circuit and method therefor for a phase locked loop

摘要

An improved phase synchronization circuit (301) and method therefor for a phase locked loop (300). Each of a divided reference frequency signal (206) and a feedback signal (209) is held in a predetermined state. The divided reference frequency signal (206) is enabled responsive to the phase of a reference frequency signal (115). A phase relationship between the reference frequency signal (115) and an output frequency signal (116 or 117) is determined. The feedback signal (209) is enabled responsive to enabling the divided reference frequency signal (206) and the determined phase relationship. The present invention advantageously provides a rapid and accurate phase synchronization for the PLL (300) with minimum additional hardware and without introducing phase error into the PLL (300).