发明名称 VIDEO SIGNAL PROCESSOR
摘要 PURPOSE:To reduce quantization distortion in the case of performing high- efficiency coding to a video signal, which is sampled at a different phase for each line, for the unit of a block. CONSTITUTION:Based on a digital signal from an A/D converter 2, an inter- frame subsampling phase is read by a phase detector 201. When switch 3 is changed over to A, a frame memory 8 is used for write. A write address generator 203 distinguishedly generates a write address corresponding to the phase detected by the phase detector 201, and the address is supplied onto the frame memory 8 by an address selector 6. When the signal of one frame is written in the frame memory 8, the switch 3 is changed over to B, and the signal of the next frame is written in a frame memory 9. At the same time, a switch 10 is changed over to A, and reading is started. Concerning the reading, an address generated by a read address generator 5 is supplied to the frame memory 8 by the address selector 6.
申请公布号 JPH07162847(A) 申请公布日期 1995.06.23
申请号 JP19930302616 申请日期 1993.12.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HORI RYUICHI;OTAKA HIDEKI
分类号 H04N19/119;H04N7/24;H04N19/00;H04N19/136;H04N19/176;H04N19/196;H04N19/423;H04N19/59;H04N19/60;H04N19/85;H04N19/91 主分类号 H04N19/119
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