| 摘要 |
PURPOSE:To provide a load line driver which can stably operate a memory cell even at a lower power source voltage while holding a high speed of a Bi-CMOS. CONSTITUTION:A PMOSFET Q11, an NMOSFET Q12 and an NMOSFET Q13 are provided between a positive side power source VDD and a negative side power source VSS, an input line IN, a word line WL and a gate are connected as prescribed to drive the word line. At the time of operating the WL, an 'H' level is fully swung, and hence a cell current is not abruptly reduced at the time of dropping the power source voltage, and high speed of a Bi-CMOS is maintained. A lowest operating power source voltage becomes the same as the ML driving by a MOS driver to obtain stability of the operation. In the case of a word line delay, a delay of the CMOS driver is shortened since the Bi-CMOS driver is used. The 'H' output is obtained from the PMOSFET Q11, and the 'L' output is formed of n-p-n Tr, and hence fall of the WL can be set faster than its rise. |
