发明名称 CLOCK SUPPLY CIRCUIT FOR LOGIC CIRCUIT OF OTHER SOURCE SUPPLY
摘要 The circuit with simple structure includes a first power source(VDD1), a clock generator(50) generating the clock with specific frequency, first(61) and second(62) logic circuits receiving the clock, and a leakage current cutting-off circuit(70) connected between the second logic circuit and the junction of the clock generator and the first logic circuit. The leakage current cutting-off circuit includes a second power source(VDD2), a diode(D1), a resistor(R4), and a buffer(IC11).
申请公布号 KR950006740(B1) 申请公布日期 1995.06.22
申请号 KR19930012128 申请日期 1993.06.30
申请人 DAEWOO TELECOM. CO., LTD. 发明人 PARK, SANG - WON
分类号 H03K3/00;(IPC1-7):H03K3/00 主分类号 H03K3/00
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