SEPARATE IDDQ-TESTING OF SIGNAL PATH AND BIAS PATH IN AN IC

摘要

An IC is tested through IDDQ-measurements. The IC's substrate comprises a region of a conductivity type with a supply node for supply of the circuit and with a biasing node for connection to a biasing voltage to bias the region. IDDQ-testing of the circuit is conducted while the supply node and the biasing node are galvanically disconnected to separate the contribution to the quiescent current from the circuit functionality features from the contribution to the quiescent current from the biasing features.