| 摘要 |
<p>An ADC, comprising an internal DAC, driven by a successive approximation SAR, and a comparator, is provided with a correction logic circuit that controls the execution of a verifying and correcting routine at the end of each conversion routine. Master-Slave cells that compose the SAR are provided with a dedicated circuitry, responding to said correction control circuit, for confirming, incrementing or decrementing the bit stored in the cell by at least an LSB. An extremely simple routine, performed at the end of each conversion cycle, permits to correct incorrectly converted digital data because of the occurrence of missing codes in the internal DAC. The corrector does not require the use of memories and/or analog circuits and is very cost-effective and permits to greatly improve production yield of complex devices containing ADCs. <IMAGE></p> |
