| 摘要 |
A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage. Each of the state hold circuits has the following truth table: -A B Qn + 1 -0 0 1 or 0 -0 1 Qn -1 0 Qn -1 1 0 or 1 - wherein A and B designate the respective logic level signals applied to the first and second input terminals and Qn+1 designates the respective logic level of the resultant, current output signal produced at the output terminal in response to the corresponding, current logic levels input signals A and B, Qn representing that the prior logic level output signal is maintained as the current logic level output signal.
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