| 摘要 |
PURPOSE:To reduce the amount of failure detection hardware, to the extent that the failure detection rate can not be deteriorated, by producing the parity bit through a part of logic circuit duplexed and by performing checking, in the failure detection of data processors. CONSTITUTION:The data in two registers among the registers 21 to 23 holding the data added with the parity bit P are selected with the register selection circuit 24 and are given to the binary adders 5, 12 and to the parity check circuit 27. The presence of error in the input data is obtained at the output of the check circuit 27, and the data adding the parity bit to the result of operation of the binary adders 5, 12 are stored in the register 26. The data in the register 26 is given to the check circuit 27 and the presence of failure in the binary adders 5,12, parity generation circuit 25, register 26 and a series of logic circuit in operation is obtained at the output of the check circuit 27. |
