Single PAL circuit generating system clock and control signals to minimize skew

摘要

The invention is for improving the performance of a microprocessor system by reducing the skew between the system clock and critical control signals. Reduction in this skew reduces or eliminates the need for waitstates on data accesses to random access memory devices thereby improving system performance. A clock PAL is programmed to function as an asynchronous state machine to generate the clock signals and the memory device chip select. A clock source from an oscillator is input to the PAL. This clock source is buffered by the PAL and presented at the PAL outputs as the system clock. The memory device chip select is also generated inside this PAL using the source clock and other signals generated inside the PAL.