发明名称 |
Test interface for a digital circuit |
摘要 |
A test interface is disclosed that is added to a digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.
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申请公布号 |
US5426649(A) |
申请公布日期 |
1995.06.20 |
申请号 |
US19940332510 |
申请日期 |
1994.10.31 |
申请人 |
AG COMMUNICATION SYSTEMS CORPORATION |
发明人 |
BLECHA, JR., JOHN F. |
分类号 |
G01R31/28;G01R31/317;G06F11/273;(IPC1-7):H04B17/00;G06F11/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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