Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines

摘要

A synchronous dynamic random access memory device allows an external device to sequentially access read-out data bits in synchronous with a system clock signal, and a column addressing system incorporated in the synchronous dynamic random access memory device forms a plurlaity of pipeline stages together with an input/output unit for sequentially supplying data bits to a data port in response to a column address internally incremented in synchronism with the system clock signal, thereby propagating the data bits through a single data bus.