MULTIPLYING METHOD AND CIRCUIT

摘要

The method rounds off without an addition of a special circuit and a delay of an arithmetic speed because a round off carry is inputted to carry input terminals. It comprises; (i) the 1st stage at which a n-bit multiplier is multiplied partially by each bit of a m-bit multiplicand and m pieces of multiplying result are generated; (ii) a 2nd stage at which a round-off-carry operation is executed with a partial value to be rounded off within the m pieces of multiplying result at the 1st stage; (iii) a 3rd stage at which the result of the 2nd stage and the remains, excluded of the value used in 2nd stage, of the 1st stage are added and a final result is caluculated.