| 摘要 |
<p>PURPOSE:To enhance a hit rate of a cache, and further, to accelerate an access time. CONSTITUTION:A DRAM memory cell array 1 being a main memory and an SRAM memory cell array 12 being a cache memory are divided to plural blocks in the same plural column unit. Information read out from the main memory in block unit is transferred to the SRAM memory cell array 12 through a sense amplifier part 4, a block transfer gate part 11, an internal I/O band 41 and a weigh transfer gate part 42. In the transferring, the information in block is transferred to either block of the SRAM memory array by a weigh decoder 14.</p> |
