发明名称 HIGH FREQUENCY AMPLIFIER INTEGRATED CIRCUIT AND ITS DRAIN BIAS CIRCUIT
摘要 PURPOSE:To reduce an output voltage of a drain power supply and power consumption by applying a drain bias directly to a drain of a FET provided between input an output matching circuits so as to eliminate a loss due to a voltage drop caused by the insertion of the output side matching circuit. CONSTITUTION:A drain bias terminal 12, output and input side matching circuits 13, 14, MMIC input output terminals 16,17 and a FET 11 connecting to the circuits 13, 14 are formed on a semiconductor substrate 10. Input/output DC cut-off capacitors 18, 19 are connected to the terminals 16, 17, and the FET 11 and a terminal 111 connecting to the terminal 12 form a drain bias circuit. Thus, a loss of a voltage drop due to the insertion of the circuit 13 is avoided and a DC equivalent circuit of the drain bias circuit is only a drain-source resistance of the FET 11. Thus, a drain bias is applied to the terminal 111 directly, a low voltage is adopted for the voltage of a drain power supply and power consumption of an amplifier is reduced.
申请公布号 JPH07154159(A) 申请公布日期 1995.06.16
申请号 JP19930299572 申请日期 1993.11.30
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIDA KAORU;IKEDA HIKARI;KOSUGI HIROAKI;KUNIHISA TAKETO;YOKOYAMA TAKAHIRO;ISHIKAWA OSAMU
分类号 H03F1/02;H03F3/195;H03F3/60;(IPC1-7):H03F3/195 主分类号 H03F1/02
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