COMPUTER SYSTEM FOR CONTROL OF PERIPHERAL- BUS CLOCK SINGNAL AND ITS METHOD

摘要

PURPOSE: To provide a system and a method for controlling peripheral bus clock signals. CONSTITUTION: Before the stoppage of the peripheral bus clock signals, indicator signals are generated by a clock control circuit (120). A slave device generates clock request signals when the peripheral bus clock signals are kept requested. The clock control circuit receives them and prevents the peripheral bus clock signals from being stopped. When an alternate bus master (108; 110) requires the control of a peripheral bus (102) in stopping the peripheral bus clock signals, the alternate bus master can be constituted so as to assert the clock request signals for the restart of the peripheral bus clocks. The signals are sent to the peripheral bus and the clock control circuit receives them and restarts the peripheral bus clock signals. The alternate bus master can generate bus request signals synchronized with the peripheral bus clock signals so as to obtain enabling signals from a bus arbiter unit (106).