| 摘要 |
<p>PURPOSE:To provide a semiconductor storage provided with a simple cache system improving a cache hit rate. CONSTITUTION:A memory cell array 5 is divided to four pieces of blocks B1-B4, and transfer gates 31 (31a-31d) and data registers 32 (32a-32d) are inserted between a sense amplifier 6 and an I/O switch 9 corresponding to the blocks B1-B4. The transfer gates 31 and the data registers 32 are provided by the same pieces of the number of columns in respective blocks of the memory cell array 5 in block, and respective transfer gates 31 are controlled by a block decoder 34 through a control line L1. Thus, by the conduction/nonconduction of the transfer gate 31, whether or not the data of the memory cell array 5 are transferred to the corresponding data register 32 through the sense amplifier 6 in block is decided.</p> |
