发明名称 PULSE DELAY CIRCUIT
摘要 <p>PURPOSE:To delay a pulse signal from a rising edge and a trailing edge accurately and equally. CONSTITUTION:The circuit is provided with a signal source 8 generating a pulse signal, an integration circuit 9 provided with a resistor 11 and a capacitor 12 and whose charge/discharge time constants are equal to each other, a comparator 13 comparing an output signal of the integration circuit 9 with a reference voltage of a reference power supply 14, and a rapid charging circuit 15 rapidly charging the capacitor 12 up to a peak level of the pulse signal and a delayed pulse signal is obtained from an output terminal of the comparator 13.</p>
申请公布号 JPH07154220(A) 申请公布日期 1995.06.16
申请号 JP19930300598 申请日期 1993.11.30
申请人 SANYO ELECTRIC CO LTD 发明人 UEKI KEIJIRO
分类号 H03K5/13;(IPC1-7):H03K5/13 主分类号 H03K5/13
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